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typical connection half-bridge driver features floating channel designed for bootstrap operation fully operational to +600 v tolerant to negative transient voltage, dv/dt immune gate drive supply range from 10 v to 20 v undervoltage lockout for both channels 3.3 v, 5 v, and 15 v input logic compatible cross-conduction prevention logic matched propagation delay for both channels high-side output in phase with in input logic and power ground +/- 5 v offset internal 500 ns deadtime, and programmable up to 5 s with one external r dt resistor lower di/dt gate driver for better noise immunity the dual function dt/sd input turns off both channels rohs compliant irs21091(s)pbf data sheet no. pd60311 v offset 600 v max. i o +/- 120 ma / 250 ma v out 10 v - 20 v t on/off (typ.) 750 ns & 200 ns deadtime 540 ns product summary www.irf.com 1 description the irs21091 is a high voltage, high speed power mosfet and igbt driver with dependent high- and low-side referenced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic construction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. the floating channel can be used to drive an n-channel power mosfet or igbt in the high-side configuration which operates up to 600 v. (refer to lead assignments for correct configuration). these dia- grams show electrical connec- tions only. please refer to our application notes and designtips for proper circuit board layout. v cc v b v s ho lo com in dt/sd dt/sd in up to 600 v to load v cc packages 8 lead soic irs21091s 8 lead pdip irs21091
irs21091(s)pbf www.irf.com 2 symbol definition min. max. units v b high-side floating absolute voltage -0.3 625 v s high-side floating supply offset voltage v b - 25 v b + 0.3 v ho high-side floating output voltage v s - 0.3 v b + 0.3 v cc low-side and logic fixed supply voltage -0.3 25 v lo low-side output voltage -0.3 v cc + 0.3 dt/sd programmable deadtime and shutdown pin voltage v ss - 0.3 v cc + 0.3 v in logic input voltage (in & dt/s d) v ss - 0.3 v cc + 0.3 dv s /dt allowable offset supply voltage transient 50 v/ns (8 lead pdip) 1.0 p d package power dissipation @ t a +25 c (8 lead soic) 0.625 (8 lead pdip) 125 rth ja thermal resistance, junction to ambient (8 lead soic) 200 t j junction temperature 150 t s storage temperature -50 150 t l lead temperature (soldering, 10 seconds) 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. v c c/w w
irs21091(s)pbf www.irf.com 3 dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, c l = 1000 pf, t a = 25 c, unless otherwise specified. symbol definition min. typ. max.unitstest conditions t on turn-on propagation delay 750 950 v s = 0 v t off turn-off propagation delay 200 280 v s = 0 v or 600 v t sd shutdown propagation delay 550 715 mt delay matching, hs & ls turn-on/off 0 70 t r turn-on rise time 100 220 t f turn-off fall time 35 80 dt deadtime: lo turn-off to ho turn-on(dt lo-ho) & 400 540 680 r dt = 0 w ho turn-off to lo turn-on (dt ho-lo) 4 5 6 s r dt = 200 k w mdt deadtime matching = dt lo - ho - dt ho-lo 0 60 r dt = 0 w 0 600 r dt = 200 k w ns ns note 1: logic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). v b high-side floating supply absolute voltage v s + 10 v s + 20 v s high-side floating supply offset voltage (note 1) 600 v ho high-side floating output voltage v s v b v cc low-side and logic fixed supply voltage 10 20 v lo low-side output voltage 0 v cc v in logic input voltage (in & dt/sd) v ss v cc dt/sd programmable deadtime and shutdown pin voltage v ss v cc t a ambient temperature -40 125 c symbol definition min. max. units recommended operating conditions the input/output logic timing diagram is shown in fig.1. for proper operation the device should be used within the recommended conditions. the v s offset rating is tested with all supply biased at a 15 v differential. v v s = 0 v
irs21091(s)pbf www.irf.com 4 static electrical characteristics v bias (v cc , v bs ) = 15 v, and t a = 25 c unless otherwise specified. the v il , v ih, and i in parameters are referenced to com and are applicable to the respective input leads: in and dt/sd. the v o , i o, and r on parameters are referenced to com and are applicable to the respective output leads: ho and lo. symbol definition min. typ.max.unitstest conditions v ih logic 1 input voltage for ho & logic 0 for lo 2.5 v il logic 0 input voltage for ho & logic 1 for lo 0.8 v sd,th dt/sd input threshold 11.5 13 14.5 v oh high level output voltage, v bias - v o 0.05 0.2 v ol low level output voltage, v o 0.02 0.1 i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 20 75 130 in = 0 v or 5 v i qcc quiescent v cc supply current 0.4 1.0 1.6 ma in = 0 v or 5 v r dt = 0 w i in+ logic 1 input bias current 5 20 in = 5 v, dt/sd = 0 v i in- logic 0 input bias current 5 in = 0 v, dt/sd = 5 v v ccuv+ v cc and v bs supply undervoltage positive going 8.0 8.9 9.8 v bsuv+ threshold v ccuv- v cc and v bs supply undervoltage negative going 7.4 8.2 9.0 v bsuv- threshold v ccuvh hysteresis 0.3 0.7 v bsuvh i o+ output high short circuit pulsed current 120 290 v o = 0 v, pw 10 s i o- output low short circuit pulsed current 250 600 v o = 15 v,pw 10 s v a v a ma v cc = 10 v to 20 v i o = 2 ma lead assignments 8 lead pdip 8 lead soic 1 2 3 4 8 7 6 5 v cc in dt/sd com v b ho v s lo IRS21091PBF irs21091spbf 1 2 3 4 8 7 6 5 v cc in dt/sd com v b ho v s lo
irs21091(s)pbf www.irf.com 5 functional block diagrams uv detect delay com lo vcc in vs ho vb pulse filter hv level shifter r r s q uv detect pulse generator vss/com level shift vss/com level shift deadtime dt/sd lead definitions symboldescription in logic input for high-side and low-side gate driver outputs (ho and lo), in phase with ho dt/sd programmable deadtime lead,disables input/output logic when tied to v cc v b high-side floating supply ho high-side gate drive output v s high-side floating supply return v cc low-side and logic fixed supply lo low-side gate drive output com low-side return
irs21091(s)pbf www.irf.com 6 figure 2. switching time waveform definitions figure 4. deadtime waveform definitions in ho 50% 50% 90% 10% lo 90% 10% dt lo-ho dt lo-ho mdt= - dt ho-lo dt ho-lo in (ho) t r t on t f t off lo ho 50% 50% 90% 90% 10% 10% in (lo) figure 5. delay matching waveform definitions ho 50% 50% 10% lo 90% mt ho lo mt in (lo) in (ho) figure 1. input/output timing diagram figure 3. shutdown waveform definitions dt/sd ho lo 50% 90% tsd in ho lo dt/sd
irs21091(s)pbf www.irf.com 7 500 700 900 1100 1300 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o n p r o p a g a t i o n d e l a y ( n s ) typ. max . figure 6a. turn-on propagation delay 500 700 900 1100 1300 10 12 14 16 18 20 v bias supply voltage (v) t u r n - o n p r o p a g a t i o n d e l a y ( n s ) typ. max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o f f p r o p a g a t i o n d e l a y ( n s ) max. typ. figure 7a. turn-off propagation delay 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) t u r n - o f f p r o p a g a t i o n d e l a y ( n s ) figure 7b. turn-off propagation delay typ. max. figure 6a. turn-on propagation delay vs. temperature figure 6b. turn-on propagation delay vs. supply voltage figure 7a. turn-off propagation delay vs. temperature figure 7b. turn-off propagation delay vs. supply volta ge note: for the following figures the v bias (v cc , v bs ) = 15 v and t a = 25 o c unless otherwise specified.
irs21091(s)pbf www.irf.com 8 f igure 9 a. t urn-on r ise time vs. temperature figure 9b. turn-on rise time vs. supply volta ge 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) sd propagation delay (ns) m ax. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) sd propagation delay (ns) typ. max. figure 8a. sd propagation delay vs. temperature figure 8b. sd propagation delay vs. supply voltage 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature( o c) t u rn -o n r i se t i me (ns) 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) t u rn -o n r i se ti me (ns) turn-on rise time (ns) turn-on rise time (ns) max. typ. typ. max.
irs21091(s)pbf www.irf.com 9 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) d e a d t i m e ( n s ) min. typ. max. 200 400 600 800 1000 10 12 14 16 18 20 v bias supply voltage (v) d e a d t i m e ( n s ) max. typ. min. figure 10a. turn-off fall time vs. temperature figure 10b. turn-off fall time vs. supply voltage figure 11a. deadtime vs. temperature figure 11b. deadtime vs. supply volta ge 0 50 100 150 200 -50 -25 0 25 50 75 100 125 temperature ( o c) t u r n - o f f f a l l t i m e ( n s ) t u r n - o f f f a l l t i m e ( n s ) max. typ. max. typ. 0 50 100 150 200 10 12 14 16 18 20 v bias supply voltage (v) t u r n - o f f f a l l t i m e n s
irs21091(s)pbf www.irf.com 10 figure 11c. deadtime vs. r dt figure 12a. logic ?1? input voltage vs. temperature figure 12b. logic ?1? input voltage vs. supply voltage 1 2 3 4 5 -50 -25 0 25 50 75 100 125 temperature (c) i n p u t v o l t a g e ( v ) 1 2 3 4 5 10 12 14 16 18 20 v bias supply voltage (v) input voltage (v) min. min. 0 1 2 3 4 5 6 7 0 50 100 150 200 r dt (kw) d e a d t i m e ( s ) typ. max. min. d e a d t i m e ( m s ) r dt (k w ) max 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 temperature (c ) l o g i c " 0 " i n p u t b i a s c u r r e n t ( a ) figure 13a. logic "0" input bias current vs. temperature
irs21091(s)pbf www.irf.com 11 s d i n p u t t h r e s h o l d ( + ) ( v ) max 0 1 2 3 4 5 6 10 12 14 16 18 20 supply voltage (v) l o g i c " 0 " i n pu t b i a s c u r r e n t ( a ) figure 13b. logic "0" input bias current vs. voltage figure 15a. high level output voltage vs. temperature 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) max. typ. -50 -25 0 25 50 75 100 125 temperature ( o c) 0.0 0.1 0.2 0.3 0.4 0.5 10 high level output voltage (v) max. 8 10 12 14 16 18 -50 -25 0 25 50 75 100 125 temperature ( o c) sd input threshold (+) (v) figure 14a. sd input positive going threshold (+) vs. temperature max. 8 10 12 14 16 18 10 12 14 16 18 20 v cc supply voltage (v) figure 14b. sd input positive going threshold (+) vs. supply voltage
irs21091(s)pbf www.irf.com 12 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) o f f s e t s u p p l y l e a k a g e c u r r e n t ( a ) max. figure 16b. low level output voltage vs. supply voltage figure 17a. offset supply leakage current vs. temperature 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bias supply voltage (v) l o w l e v e l o u t p u t v o l t a g e ( v ) max. typ. o f f s e t s u p p l y l e a k a g e c u r r e n t ( m a ) figure 15b. high level output voltage vs. supply volta ge figure 16a. low level output voltage vs. temperature 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bias supply voltage (v) high level output voltage (v) max. typ. 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 temperature ( o c) l o w l e v e l o u t p u t v o l t a g e ( v ) max. typ.
irs21091(s)pbf www.irf.com 13 figure 17b. offset supply leakage current vs. boost voltage o f f s e t s u p p l y l e a k a g e c u r r e n t ( m a ) figure 19a. v cc supply current vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c s u p p l y c u r r e n ( m a ) max. typ. min. v c c s u p p l y c u r r e n t (m a ) 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) v b s supply current (a) figure 18a. v bs supply current vs. temperature 0 100 200 300 400 500 0 100 200 300 400 500 600 v b boost voltage (v) max. 0 100 200 300 400 10 12 14 16 18 20 supply voltage (v) v b s supply current (a) figure 18b. v bs supply current vs. supply voltage typ. min. max. max. typ. min.
irs21091(s)pbf www.irf.com 14 figure 20b. logic ?1? input current vs. supply voltage 0 10 20 30 40 50 60 10 12 14 16 18 20 v cc supply voltage (v) l o g i c " 1 " i n p u t c u r r e n t ( a ) figure 21b. logic "1" input current max. typ. l o g i c 1 i n p u t c u r r e n t ( m a ) l o g i c 0 i n p u t c u r r e n t ( m a ) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 10 12 14 16 18 20 v cc supply voltage (v) v c c s u p p l y c u r r e n t ( m a ) figure 20b. v supply current max. typ. min. figure 19b. v cc supply current vs. v cc supply voltage 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 temperature ( o c) l o g i c " 1 " i n p u t c u r r e n t ( a ) typ. max. figure 20a. logic ?1? input current vs. temperature l o g i c 1 i n p u t c u r r e n t ( m a ) figure 21a. logic ?0? input current vs. temperature max. 0 2 4 6 8 10 -50 -25 0 25 50 75 100 125 temperature ( o c)
irs21091(s)pbf www.irf.com 15 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c u v l o t h r e s h o l d ( + ) ( v ) typ. max. min. figure 22. v cc undervoltage threshold (+) vs. temperature figure 21b. logic ?0? input currentt vs. supply voltage l o g i c 0 i n p u t c u r r e n t ( m a ) 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v c c u v l o t h r e s h o l d ( - ) ( v ) typ. max. min. 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 temperature ( o c) v b s u v l o t h r e s h o l d ( + ) ( v ) typ. max. min. figure 23. v cc undervoltage threshold (-) vs. temperature figure 24. v bs undervoltage threshold (+) vs. temperature max. 0 2 4 6 8 10 10 12 14 16 18 20 v cc supply voltage (v)
irs21091(s)pbf www.irf.com 16 figure 26b. output source current vs. supply voltage figure 27a. output sink current vs. temperature 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) o u t p u t s i n k c u r r e n ) typ. min. o u t p u t s i n k c u r r e n t ( m a) 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 temperature ( o c) v b s u v l o t h r e s h o l d ( - ) ( v ) typ. max. min. figure 25. v bs undervoltage threshold (-) vs. temperature 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) output source current (ma) figure 26a. output source current vs. temperature 0 100 200 300 400 500 10 12 14 16 18 20 v bias supply voltage (v) output source current (ma) typ. min. typ. min.
irs21091(s)pbf www.irf.com 17 -10 -8 -6 -4 -2 0 10 12 14 16 18 20 v bs floating supply voltage (v) v s o f f s e t s u p p l y v o l t a g e ( v ) typ. figure 27b. output sink currentt vs. supply voltage figure 28. maximum v s negative offset vs. supply voltage 0 200 400 600 800 1000 10 12 14 16 18 20 v bias supply voltage (v) o u t p u t s i n k c u r r e n typ. min. o u t p u t s i n k c u r r e n t (m a)
irs21091(s)pbf www.irf.com18 case outlines 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [.010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994. 2 . c o n t r o l l in g d im e n s io n : m il l im e t e r 3. dimensions are shown in millimeters [inc hes]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 d im e n s io n is t h e l e n g th o f l e a d f o r s o l d e r in g to a subs trate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] c a b e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 b asic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters in c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 b asic 0.635 b asic 01-6014 01-3003 01 (ms-001ab) 8 lead pdip
irs21091(s)pbf www.irf.com19 carrier tape dimension for 8soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3 .90 4.10 0.15 3 0 .161 c 11.70 12.30 0.46 0.484 d 5 .4 5 5.5 5 0. 21 4 0 .2 18 e 6 .3 0 6.5 0 0. 24 8 0 .2 55 f 5 .1 0 5.3 0 0. 20 0 0 .2 08 g 1.50 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n /a 1 8.40 n /a 0 .7 24 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 m etr ic im p erial e f a c d g a b h n ote : co ntrolling d imension in mm load ed tape feed direction a h f e g d b c tape & reel 8-lead soic
irs21091(s)pbf www.irf.com20 the soic-8 is msl2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 data and specifications subject to change without notice. 6/22/2007 leadfree part marking information lead free released non-lead free released part number date code irxxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code s 8-lead pdip IRS21091PBF 8-lead soic irs21091spbf 8-lead soic tape & reel irs21091strpbf order information

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